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1 ir22381q pbf /IR21381q ( p b f ) 3-phase ac motor controller ic features ? floating channel up to +600v or +1200v ? soft over-current shutdown turns off desaturated output ? integrated desaturation circuit ? active biasing on sensing desaturation input ? two stage turn on output for di/dt control ? integrated brake igbt driver with protection ? voltage feedback sensing function ? separate pull-up/pull-do wn output drive pins ? matched delay outputs ? under voltage lockout with hysteresis band ? programmable deadtime ? hard shutdown function description t he ir223 81 q and i r 2 13 81q a r e h i gh volta g e, 3 - p h ase igbt driver best suited for ac moto r drive applications. integrated desaturation logic provides all mo de of overcurrent protection, including ground fault protection. the sensing desaturation input is provided by active bias stage to reject noise. soft shutdown is predominantly initiated in the event of overcurrent followed by turn- off of all six outputs. a shutdown input is provided for a customized shutdown function. the dt pin allows external resistor to program the deadtime. output drivers have separate turn on/off pins with two stage turn-on output to achieve the desired di/dt switching level of igbt. voltage feedback provides accurate volt x second measurement. product summary v offset (max) 600v or 1200v i o +/- (min.) 220ma / 460ma v out 12.5v-20v brake ( i o +/- min.) 40ma/80ma deadtime asymmetry skew (max.) 125 nsec deadtime (typ. with rdt=39k ? ) 1 sec desat blanking time (typ.) 4.5sec desat filter time (typ.) 3.0sec active bias on desat input pin 90 ? dsh, dsl input voltage threshold (typ.) 8.0v soft shutdown duration time (typ.) 6.0 sec voltage feedback matching delay ti m e (ma x .) 400 nsec package 64-lead mqfp w/o 13 leads typical connection (refer to lead assignments for correct pin configuration. this diagram shows electrical connections only) vb1,2,3 dsh1,2,3 hop1,2,3 hoq1,2,3 hon1,2,3 lop1,2,3 loq1,2,3 lon1,2,3 com dsl1,2,3 vs1,2,3 ir22381q pbf vcc lin1,2,3 hin1,2,3 fault brin sd vfh1,2,3 vfl1,2,3 dsb br dt vss dc bus to controller u v w to motor 15v 33 data sheet pd60232 rev c downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 2 abso l u te maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to v ss , all currents are defined positive into any lead. the thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. symbol definition min. max. units v s high side offset voltage v b 1,2,3 - 25 v b 1,2,3 + 0.3 (ir22381) -0.3 1225 v b high side flo a ting su p ply voltage (IR21381) -0.3 625 v ho high side floating output voltage (hop, hon, hoq) v s1,2,3 - 0.3 v b 1,2,3 + 0.3 v cc low side and logic fixed supply voltage -0.3 25 com power ground v cc - 25 v cc + 0.3 v lo low side output voltage (lop, lon, loq) v com -0.3 v cc + 0.3 v in logic input voltage (hin/n, lin, brin/n, sd) -0.3 v cc + 0.3 or v ss +15 which ever is lower v flt fault/n output voltage -0.3 v cc + 0.3 v f feedback output voltage -0.3 v cc + 0.3 v dsh high side desat/feedback input voltage v b 1,2,3 - 25 v b 1,2,3 + 0.3 v dsl low side desat/feedback input voltage v cc - 25 v cc + 0.3 v br brake output voltage v com -0.3 v cc + 0.3 v dvs/dt allowable offset voltage slew rate 50 v/ns p d package power dissipation @ ta +25c 2.0 w r thja thermal resistance, junction to ambient 60 c/w t j junction temperature 125 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) 300 c recom m ended o p era t ing conditions for proper operation the device should be used within the recommended conditions. all voltage parameters are absolute voltages referenced to v ss . the v s offset rating is tested with all supplies biased at 15v differential. symbol definition min. max. units v b 1,2,3 high side floating supply voltage (note 1) v s1,2,3 +12.5 v s1,2,3 + 20 v s1,2,3 high side floating supply offset voltage (IR21381) note 2 600 (ir22381) note 2 1200 v ho 1,2,3 high side (hop/hoq/hon) output voltage v s1,2,3 v s1,2,3 + v b v lo1,2,3 low side (lop/loq/lon) output voltage v com v cc v in logic input voltage (hin/n, lin, brin/n sd) 0 v ss + 5 v cc low side supply voltage (note 1) 12.5 20 com power ground - 5 + 5 v flt fault/n output voltage 0 v cc v f feedback output voltage 0 v cc v dsh high side desat/feedback input voltage v b 1,2, 3 - 20 v b 1,2,3 v dsl low side desat/feedback input voltage v cc - 20 v cc v br br output voltage v com v cc v t a ambient temperature -40 115 c note 1: while internal circuitry is operational below the indicated supply voltages, the uv lockout disables the output drivers if th e uv thresholds are not reached. note 2: logic operational for v s from v ss -5v to v ss +600v (IR21381) or 1200v (ir22381). logic state held for v s from v ss -5v to v ss - v bs . (please refer to the design tip dt97-3 for more details). downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 3 static electrical characteristics v bias (v cc, v bs1,2,3 ) = 15v and t a = 25 c unless otherwise specified. i/o diagrams dont show esd protection circuits. pin: v cc , v ss , v b , v s symbol definition min typ max units test conditions v ccuv+ v cc1 supply undervoltage positive going threshold 10.3 11.2 12.5 v ccuv- v cc1 supply undervoltage negative going threshold 9.5 10.2 11.3 v ccuvh v cc1 supply undervoltage lockout hysteresis - 1.0 - v bsuv+ v bs supply u n dervolta g e p o sitive going t h reshold 10.3 11.2 1 1.9 v bsuv- v bs supply u n dervolta g e n e gative going t hr e sho l d 9.5 10.2 1 0.9 v bsuvh v bs supply undervoltage lockout hysteresis - 1.0 - v (IR21381q) - - 50 v b1,2,3 =v s1,2,3 = 600v i lk offset supply leakage current (ir22381q) - - 50 v b1,2,3 =v s1,2,3 = 1200v i qbs quiescent v bs supply current - 150 300 a v lin =0v,v hin =5v, dsh 1,2,3 = v s1,2,3 i qcc quiescent vcc supply current - 3 6 ma v lin =0v,v hin =5v dt=1 sec v cc /v b comparator v ss /v s v ccuv /v bsuv uv figure 1: undervoltage diagram pin: hin/n, lin, brin/n, sd the v in , v th and i in parameters are referenced to v ss and are applicable to all six channels (hop/hoq/ hon 1,2,3 and lop/loq/lon 1,2,3 ). symbol definition min typ max units test conditions v ih logic "0" input voltage (hin/n, lin, brin /n, sd)(out=lo) 2.0 - - v il logic "1" input voltage (hin/n, lin, brin/n, sd)(out=hi) - - 0.8 v t+ logic input positive going threshold (hin/n, lin, brin/n, sd) 1.2 1.6 2.0 v t- logic input negative going threshold (hin/n, lin, brin/n, sd) 0.8 1.2 1.6 ? v t logic input hysteresis(hin/n, lin, brin/n, sd) - 0.4 - v v cc = 12.5v to 20v i in+ logic "1" input bias current (hin/n, brin/n) logic "1" input bias current (lin, sd) -2 - - 85 0 140 v in = 0v v in = 5v i in- logic "0" input bias current (hin/n, brin/n) logic "0" input bias current (lin, sd) - -2 85 - 140 0 a v in = 5v v in = 0v downloaded from: http:///
ir22381q pbf /IR21381q ( p bf) 4 figure 2: hin/n, lin and brin/n diagram pin: fault/n, vfh, vfl v olvf is referenced to v ss symbol definition min typ max units test conditions v olvf vfh or vfl low level output voltage - - 0.8 v i vf = 10ma r on,vf vfh or vfl output on resistance - 60 - r on,flt fault/n low on resistance - 60 - ? ______ fault / vfl/vfh v ss internal signal r on figure 3: fault/n, vfh, vfl diagram pin: dsl, dsh, dsb v desat and i desat parameters are referenced to com and v s1,2,3 symbol definition min typ max units test conditions v desat+ high dsh 1,2,3 and dsl 1,2,3 and dsb input threshold voltage - 8.0 - v desat- low dsh 1,2,3 and dsl 1,2,3 or dsb input threshold voltage - 7.0 - v dsth ds input voltage hysteresis - 1.0 - v i ds+ high dsh, dsl, dsb input bias current - 15 - v desat = 15v i ds- low dsh, dsl input bias current - -150 - v desat = 0v i dsbr- low dsb input bias current - -250 - a v desat = 0v i dsb dsh or dsl input bias current - -11.1 - ma v desat = (v cc or v bs ) C 1v figure 4: dsh, dsl and dsb diagram downloaded from: http:///
ir22381q pbf/IR21381q ( p bf) 5 pin: hop, lop, hoq, loq the v o and i o parameters are referenced to com and vs 1,2,3 and are applicable to the respective output leads: ho 1,2,3 and lo 1,2,3 . symbol definition min typ max units test conditions v oh high level output voltage, v bias C v o (normal switching). hop=hoq, lop=loq. - - 2 v i o = -20ma i o1+ output high first stage short circuit pulsed current. hop=hoq, lop=loq 2 0 0 o =0 v , v in =1 (note 1) pw t on1 figure 16 i o2+ output high second stage short circuit pulsed current. hop=hoq, lop=loq 1 0 0 200 - ma v o =0v, v in =1 (note 1) pw 10 s note 1 : for hox ? hinx/n = 0v, for lox ? lin = 5v figure 5: hop/hoq and lop/loq diagram pin: hon, lon, ssdh, ssdl the v o and i o parameters are referenced to com and vs 1,2,3 and are applicable to the respective output leads: ho 1,2,3 and lo 1,2,3 . symbol definition min typ max units test conditions v ol low level output voltage, v o (normal switching) hon, lon - - 2 v i o = 20ma r on,ss soft shutdown on resistance (see note 2) - 500 - ? pw t ss i o- output low s h ort circuit pu l sed curr e nt 250 540 - ma v o =15v, v in =0 (note 3) pw 10 s note 2 : ssd operation only note 3 : for hox ? hinx/n = 5v, for lox ? lin = 0v figure 6: hon, lon diagram v - 350 downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 6 pin: br the v o and i o parameters are referenced to com and are applicable to br output . symbol definition min typ max units test conditions v ohb br high level output voltage, v cc - v br - - 6 i br = -20ma v olb br low level output voltage, v br - - 3 v i br = 20ma i obr+ br output high short circuit pulsed current 40 70 - v br =15v, v brin/n =0v pw 10 s i obr- br output low short circuit pulsed current 80 125 - ma v br =0v, v brin/n =5v pw 10 s ac electrical characteristics v bias (v cc, v bs ) = 15v, vs 1,2,3 =v ss , t a = 25 c and cl= 1000pf unless otherwise specified. symbol definition min. typ. max. units test conditions propagation delay characteristics t on1 turn-on first stage duration time 200 v in = 0 & 5v r l (hoq/loq)=10 ? t on turn-on propagation delay 250 550 750 t off turn-off propagation delay 250 550 750 t r turn-on rise time 80 t f turn-off fall time 25 v in = 0 & 5v v s 1,2,3 = 0 to 600 or 1200v hop=hon,lop=lon figure 7 t desat1 dsh to ho soft shutdown propagation delay at ho turn-on 4500 t desat2 dsh to ho soft shutdown propagation delay after blanking 3000 v hin = 0v, v desat = 15v, figure 11 t desat3 dsl to lo soft shutdown propagation delay at lo turn-on 4500 t desat4 dsl to lo soft shutdown propagation delay after blanking 3000 v lin = 5v v desat = 15v, figure 11 t desat5 dsb to ho hard shutdown propagation delay 3300 ns v hin = 0v, v desat = 15v, figure 11 t desat6 dsb to lo hard shutdown propagation delay 3300 v lin = 5v v desat = 15v, figure 11 t desat7 dsb to br hard shutdown propagation delay 3000 v brin = 0v v dsb = 15v, figure 11 t vfhl1,2,3 vfh high to low propagation delay 550 v desat = 15v to 0v figure 12 t vfhhl1,2,3 vfh low to high propagation delay 550 v desat = 0v to 15v figure 12 t vflh1,2,3 vfl low to high propagation delay 550 v desat = 0v to 15v figure 12 t vfll1,2,3 vfl high to low propagation delay 550 v desat = 15v to 0v figure 12 t pwvf minimum pulse width of vfh and vfl 400 v desat = 15v to 0v or 0v to 15v figure 12 downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 7 ac electrical charac teristics cont. v bias (v cc , v bs ) = 15v, v s1,2, 3 =v ss , t a = 25 c and c l = 1000pf unless otherwise specified. symbol definition min. typ. max. units test conditions propagation delay characteristics cont. t ds soft shutdown minimum pulse width of desat 3000 cl=1000pf, v ds =15v figure 8-9 t ss soft shutdown duration period 6000 t flt,desat1 dsh to fault propagation delay at ho turn-on 4800 v hin = 0v, v ds =15v, figure 11 t flt,desat2 dsh to fault propagation delay after blanking 3300 t flt,desat3 dsl to fault propagation delay at lo turn-on 4500 v lin = 5v, v ds =15v, figure 11 t flt,desat4 dsl to fault propagation delay after blanking 3000 t fltdsb dsb to fault propagation delay 3000 ns v brin/n = 0v v desat = 15v, figure 11 t fltclr lin1=lin2=lin3=0 to fault 9.0 v desat =15v, figure 11 t fault minimum fault duration period 9.0 15.0 21.0 s v desat =15v, figure 15 fltclr pending t bl ds blanking time at turn on 4500 v in = on v desat =15v, figure 11 t sd sd to output shutdown propagation delay 600 900 v in = on v desat =0v, figure 14 t en sd disable propagation delay 600 900 v in = on v desat =0v, figure 14 t onbr br output turn-on propagation 110 200 t offbr br output turn-off propagation 125 200 t rbr br output turn-on rise time 235 400 t fbr br output turn-off fall time 130 250 ns figure 7 dead-time/delay matching characteristics 800 1000 1200 figure 12, external resistor=39k ? 76 100 124 figure 12,external resistor=0k ? dt deadtime 4500 5000 5500 figure 12, external resistor=220k ? deadtime asymmetry skew, any of 125 dt=1000ns mdt dtl off1,2,3 -dth off1,2,3 figure 12 pm pwm propagation delay matching max {ton/toff} -min {ton/toff}, (ton/toff are applicable to all six channels) 125 dt=1000ns figure 12 voltage feedback delay matching, i any of 400 vm t vfhl1,2,3 , t vfhhl1,2,3 , t vfll1,2,3 , t vflh1,2,3 - any of t vfhl1,2,3 , t vfhhl1,2,3 , t vfll1,2,3 , t vflh1,2,3 ns input pulse width > 400nsec, figure 13 downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 8 figure 7: switching time waveforms figure 8: low side desat soft shutdown timing waveform downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 9 figure 9: high side desat soft shutdown timing waveform figure 10: brake desat timing waveform downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 10 figure 11: desat timing diagram downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 11 hin lin ho (hop=hoq=hon) 90% 50% 50% 10% 10% 50% lo (lop=loq=lon) 90% 50% dt dt dtl off dth off figure 12: internal dead-time timing v desat- 90% 10% 10% 90% v b1,2,3 v s1,2,3 dsh 1,2,3 v b1,2,3 v s1,2,3 dsl 1,2,3 v cc v cc v ss v ss vfh 1,2,3 vfl 1,2,3 t vfhl1,2,3 t vfhh1,2,3 t vflh1,2,3 t vfll1,2,3 v desat+ v desat+ v desat- figure 13: voltage feedback timing downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 12 figure 14: shutdown timing figure 15: fault duration with pending faultclear waveform (see paragraph 1.4.5 on page 21) figure 16 : output source current downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 13 lead definitions symbol description v cc low side supply voltage v ss logic ground hin 1,2,3 /n logic inputs for high side gate driver outputs (hop 1,2,3 /hoq 1,2,3 /hon 1,2,3 ) lin 1,2,3 logic input for low side gate driver outputs (lop 1,2,3 /loq 1,2,3 /lon 1,2,3 ) fault/n fault output (latched and open drain) sd shutdown input dt programmable deadtime resistor pin dsb brake igbt desaturation protection input brin/n logic input for brake driver figure 17: package pin out l e ad a ss i gn m e nts downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) br brake driver output com brake and low side drivers return vb 1,2,3 high side gate driver floating supply hop 1,2,3 high side driver sourcing output hoq 1,2,3 high side driver boost sourcing output hon 1,2,3 high side driver sinking output dsh 1,2,3 igbt desaturation protection input and high side voltage feedback input (see par. 1.4.3 on page 19) vs 1,2,3 high voltage floating supply return lop 1,2,3 low side driver sourcing output loq 1,2,3 low side driver boost sourcing output lon 1,2,3 low side driver sinking output dsl 1,2,3 igbt desaturation protection input an d low side voltage feedback input (see par. 1.4.3 on page 19) vfh 1,2,3 high side voltage feedback logic output vfl 1,2,3 low side voltage feedback logic output l e ad def i nitions continued s y mbol de s cription 1 4 downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 15 functional block diagram schmitt trigger input & shoot t hrough prevention fault logic schmitt trigger input & shoot t hrough prevention schmitt trigger input & shoot t hrough prevention 100nsec minimum deadtime 100nsec minimum deadtime 100nsec minimum deadtime level shifters level shifters level shifters latch local desat protection soft shutdown voltage feedback uv det ect uv detect hin1 hin2 hin3 shutdown fault hin1 lin1 hin2 lin2 hin3 lin3 lop1 lon1 lon2 lop2 lop3 lon3 com driver driver driver driver driver driver hop3 hon3 vs3 vb3 vb2 hop2 hon2 vs2 vb1 hop1 hon1 vs1 vcc vss dsl1 dsl2 dsl3 dsh1 vfb latch local desat protection soft shut down voltage feedback uv det ect latch local desat protection soft shut down voltage feedback uv det ect dsh2 dsh3 soft shutdown di/dt control vfb shutdown shutdown vfb hin1 hin2 hin3 di/dt control di/dt control di/dt control di/dt control di/dt control local desat protection soft shutdown voltage feedback local desat protection soft shut down voltage feedback local desat protection soft shut down voltage feedback lin1 lin2 lin3 vfh3 vfh2 vfh1 vfl1 vfl2 vfl3 brake driver br hoq1 hoq2 hoq3 loq1 lop2 loq3 desat det ect ion dsb shutdown clear logic to low side logic brin dt sd downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 16 state diagram stable states ? fault ? normal operation ? undervoltage v cc ? shutdown (sd) ? undervoltage v bs temporary states ? soft shutdown system variables ? fault clear indicates: lin1=lin2=lin3=0 ? hin/n /lin/brin/n ? uv_vcc ? uv_vbs ? dsh/l, dsb ? sd note 1 : a change of logic value of the signal labeled on lines (system variable) generates a state transition. note 2 : exiting from undervoltage v bs state, the ho goes high only if a falling edge ev ent happens in hin/n. downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 17 logic table output drivers status description ho/lo/br status hop/lop hoq/loq hon/lon br 0 hiz hiz 0 0 1 1 1 (after t on1 ) hiz 1 ssd hiz hiz ssd pull- down n/a lo/ho/br output follows inputs inputs output under voltage driver outputs operation hin/n lin brin/n sd fault/n vcc vbs ho lo br 0 0 brin/n 0 1 no no 1 0 br 1 1 brin/n 0 1 no no 0 1 br normal operation 1 0 brin/n 0 1 no no 0 0 br anti shoot through 0 1 brin/n 0 1 no no 0 0 br shut down x x brin/n 1 1 x x 0 0 br x ( note1 ) lin brin/n 0 1 no yes 0 lo br under voltage x x x 0 1 yes x 0 0 0 soft sd (after dsl/h) x x brin/n x 1 no no ssd ssd br hard sd (after dsb) x x x x 0 no no 0 0 0 fault x x ( note2 ) x x 0 no no 0 0 0 fault clear x ? hin/n lin1= lin2= lin3= 0 brin/n x (after t fltclr ) no no 0 ? ho 0 br note1 : unless in anti shoot through condition. note2 : fault duration is at least t fault when lin1=lin2=lin3=0. device stay s in fault condition in all other cases. downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 18 timing and logic state diagrams description the following picture (figure 18) sh ows the input/output logic diagram. figure 18: i/o timing diagram referred to timing diagram of figure 18: a. when the input signals are on together the outputs go off (anti-shoot through). b. the ho signal is on and the high side igbt desaturates, the ho turn off softly. fault goes low. while in ssd, if lin goes up, lo does not change (freeze). c. when fault is latched low (see fault section) it can be disabled by lin1=lin2=lin3=0 condition. d. sd disable ho and lo outputs. e. the lo signal is on and the low side igbt desaturates, the low side behaviour is the same as described in point b. f. as c. g. as d. h. as a. i. the br signal is on and the brake igbt desaturates. the driver goes in fault condition tuning off all the igbts (hard shut down). downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 19 1 features description 1.1 start-up sequence device starts in fault condition at power-up unless fault clear condition is forced (i.e. lin1=lin2=lin3=0 for at least t fltclr C in this case fault is asserted for t fltclr , then resets). in fault condition driver outputs are insensitive to inputs: any noise on input pins is then rejected during system power-up. as soon as the controller awakes, a fault clear action can be taken to enter the normal operating condition. 1.2 normal operation mode after clearing fault condition and supplies are stable the device becomes fully operative (see grey blocks in the state diagram). hin/n 1,2,3 , lin 1,2,3 and brin/n produce driver outputs to switch accordingly, while the input logic checks the input signals preventing shoot-through events and including dead-time (dt). 1.3 shut down the system controller can asynchronously command the shutdown through the 3.3 v compatible cmos i/o sd pin. this event is not latched. 1.4 fault management ir22381 is able to manage both the supply failure (undervoltage lockout on both low and high side circuits) and the desaturation of power transistors connected to its drivers outputs. 1.4.1 undervoltage (uv) the undervoltage protection function disables the output stage of each driv er preventing the power device being driven with too low voltages. both the low side (v cc supplied) and the floating side (v bs supplied) are controlled by a dedicate undervoltage function. undervoltage event on the v cc (when v cc < uv vcc- ) generates a diagnostic signal by forcing fault pin low (see fault section and figure 20). this event di sables both low side and floating drivers and the diagnostic signal holds until the under voltage condition is over. fault condition is not latched and the fault pin is released once v cc becomes higher than uv vcc+ . the undervoltage on the v bs works disabling only the floating driver. undervoltage on v bs does not prevent the low side driver to activate its output nor generate diagnostic signals. v bs undervoltage condition (v bs < uv vbs- ) latches the high side output stage in the low state. v bs must be reestablished higher than uv vbs+ to return in normal operating mode. to turn on the floating driver h in must be re-asserted high (rising edge event on h in is required). 1.4.2 4.2 power devices desaturation different causes can generate a power inverter failure: phase and/or rail supply short-circuit, overload conditions induc ed by the load, etc in all these fault conditions a large current increase is produced in the igbt. the ir22381/IR21381 fault detection circuit monitors the igbt emitter to collector voltage (v ce ) by means of an external high voltage diode. high current in the igbt may cause the transistor to desaturate, i.e. v ce to increase. once in desaturation, the current in power transistor can be as high as 10 times the nominal current. whenever the transistor is switched off, this high current generates relevant voltage transients in the power stage that need to be smoothed out in order to avoid destruction (by over-voltages). the ir22381/IR21381 gate driver accomplish the transients control by smoothly turning off the desaturated transistor by means of the lon pin activating a so called soft shutdown sequence (ssd). 1.4.3 desaturation detection: dsh/l and dsb pin function figure 19 shows the struct ure of the desaturation sensing and soft shutdown block. this configuration is the same for both high and low side output stages. downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 20 figure 19: high and low side output stage for channels 1, 2, 3 uv detect latch local desat protection soft shutdown voltage feedback hin1 vb1 hoq1 hop1 hon1 vs1 dsh1 di/dt control driver level shifters hin1 shutdown vfh1 input latch hold 100ns minimum deadtime schmitt trigger input & shoot through prevention ____ hin1 lin1 hold latch oneshot local desat protection soft shutdown voltage feedback lin1 loq1 lop1 lon1 dsl1 di/dt control driver lin1 vfl1 br di/dt control driver dsb desat protection soft shutdown desat h1 desat l1 desat h2 desat h3 desat l2 desat l3 fault duration (t fault ) clear logic lin2 lin3 _____ fault vss uv detect com vcc rs q fault logic hard shutdown shutdown shutdown ____ brin uv_vcc figure 20: fault management diagram downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 21 the external sensing diode should have bv>600v (or 1200v depending on application) and low stray capacitance (in order to minimize noise coupling and switching delays). the diode is biased by a dedicated circuit for igbt driver outputs (see the active-bias section) and by a pull-up resistor for brake output. when v ce increases, the voltage at dsh/l pin increases too. being internally biased to the local supply, dsh/l or dsb voltage is automatically clamped. w hen dsh/l or dsb exceed the v desat+ threshold the comparator triggers (see figure 19). comparator output is filtered in order to avoid false desaturation detection by externally induced noise; pulses shorter than t ds are filtered out. to avoid detecting a false desaturation during igbt turn on, the desaturation circuit is disabled by a blanking signal (t bl , see blanking block in figure 19). blanking time is the estimated maximum igbt turn on time and must be not exceeded by proper gate resistance sizing. when the igbt is not completely saturated after t bl , desaturation is detected and the driver will turn off. 1.4.4 ssd and fault management output bridge desaturation event implies a large amount of current. for that reason, ir22381 turn off strategy is based on soft shutdown. eligible desaturation signals coming from dsh/l inputs initiate the soft shutdown sequence (ssd). while in ssd, the ssd pull-down is activated (r on,ss for t ss C see figure 19) to turn off the igbt through hon/lon. figure 20 shows the fault management circuit. in this diagram desat_h1,2,3 and desat_l1,2,3 are the internal signals triggered by the desaturation event. ir22381 accomplishes output bridge turn off in the following way: - if the desaturated igbt is a low side, all the low side igbts are softly turned off (ssd), while the high side igbts are kept in the state they were just before the desaturation event. - if the desaturated igbt is a high side, it is soflty turned off simultaneously with all the low side igbts. while the remaining hs igbts are kept in the state they were just before the desaturation event. in any case, after the soft shutdown period (t ss ), all igbts are hardly shut down (brake igbt included). desaturation event generates a fault signal (see figure 11) that is latched until fault clear condition is verified. it must be noted that while in soft shut down, both under voltage fault and external shut down (sd) are masked until the end of ssd. desaturation protection is working independently by the other control pins and it is disabled only when the output status is off. brake igbt brake desaturation causes a hard shutdown for all the igbts. fault condition is asserted and hold until cleared by controller. 1.4.5 fault clear fault is cleared by forcing low simultaneously lin1, lin2 and lin3 for at least t fltclr . when lin inputs are simultaneously low and a desaturation event happens, fault is activated for a minimum amount of time of t fault . 1.5 active bias for the purpose of sensi ng the power transistor desaturation the collector voltage is read by an external hv diode. the di ode is normally biased by an internal pull up resistor connected to the local supply line (v b or v cc ). when the transistor is on the diode is conducting and the amount of current flowing in the circuit is determined by the internal pull up resistor value. in the high side circuit, the desaturation biasing current may become relevant for dimensioning the bootstrap capacitor (see figur e 23). in fact, too low pull up resistor value may result in high current discharging significantly the bootstrap capacitor. for that reason typical pull up resistor are in the range of 100 k ? . this is the value of the internal pull up. while the impedance of dsh/dsl pins is very low when the transistor is on (low impedance path through the external diode down to the power transistor), the impedance is only controlled by the pull up resistor when the transistor is off. in that case relevant dv/dt applied by the power transistor during the commutation at the output results in a considerable current injected through the stray capacitance of the diode into the desaturation detection pin (dsh/l). this coupled noise may be easily reduced using an active bias for the sensing diode. an active bias structure is available dsh/l pin. the dsh/l pins present an active pull-up respectively to vb/vcc, and a pull-down respectively to vs/com. the dedicated biasing circuit reduces the impedance on the dsh/l pin when the voltage exceeds the v desat threshold (see figure 21). this low impedance helps in rejecting the noise providing the current inject by the parasitic capacitance. when the downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 22 power transistor is fully on, the sensing diode gets forward biased and the voltage at the dsh/l pin decreases. at this point the biasing circuit deactivates, in order to reduce the bias current of the diode as shown in figure 21. figure 21: r dsh/l active biasing 1.6 output stage the structure is shown in figure 19 and consists of two turn on stages (connected to hop/lop and hoq/loq), one turn off stage for normal operation and one turn off stage for ssd operation (both connected to hon/lon). when the driver turns on the igbt (see figure 16), a first stage is constantly activated (hop/lop) while an additional stage is maintained active only for a limited time (t on1 , hoq/loq). this feature boost the total driving capability in order to accommodate both fast gate charge to the plateau voltage and dv/dt control in switching. at turn off, a single n-channel sinks up to 460ma (i o- ) and offers a low impedance path to prevent the self- turn on due to the parasiti c miller capacitance in the power switch. 1.7 voltage feedback voltage feedback pins prov ide information about the state of the corresponding igbt by means of sensing its collector. the v desat threshold discriminates whether the sensed igbt can be considered on (dsh/l < v desat ) or off (dsh/l > v desat ). igbt state information is then sent to vfh/l 1,2,3 open collector outputs, which are tied to vss ground. see figure 22 for functional details. figure 22 : voltage feedback functional diagram downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 23 2 sizing tips 2.1 bootstrap supply the v bs1,2,3 voltage provides the supply to the high side drivers circuitry of the ir22381/IR21381. v bs supply sit on top of the v s voltage and so it must be floating. the bootstrap method to generate v bs supply can be used with ir22381/IR21381 high side drivers. the bootstrap supply is formed by a diode and a capacitor connected as in figure 23. ir22381q or IR21381q figure 23: bootstrap supply schematic this method has the advantage of being simple and low cost but may force some limitations on duty- cycle and on-time since they are limited by the requirement to refresh the charge in the bootstrap capacitor. proper capacitor choice can reduce drastically these limitations. bootstrap capacitor sizing to size the bootstrap capacitor, the first step is to establish the minimum voltage drop ( ? v bs ) that we have to guarantee when the high side igbt is on. if v gemin is the minimum gate emitter voltage we want to maintain, the voltage drop must be: ceon ge f cc bs v v v v v ? ? ? ? min under the condition: ? > bsuv ge v v min where v cc is the ic voltage supply, v f is bootstrap diode forward voltage, v ceon is emitter-collector voltage of low side igbt and v bsuv- is the high-side supply undervoltage negative going threshold. now we must consider the influencing factors contributing v bs to decrease: ? igbt turn on required gate charge ( q g ); ? igbt gate-source leakage current ( i lk_ge ); ? floating section quiescent current ( i qbs ); ? floating section leakage current ( i lk ) ? bootstrap diode leakage current ( i lk_diode ); ? desat diode bias when on ( i ds- ) ? charge required by the internal level shifters ( q ls ); typical 20nc ? bootstrap capacitor leakage current ( i lk_cap ); ? high side on time ( t hon ). i lk_cap is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are used. it is strongly recommend using at least one low esr ceramic capacitor (paralleling electrolytic and low esr ceramic may result in an efficient solution). then we have: + + + + = qbs ge lk ls g tot i i q q q _ ( hon ds cap lk diode lk lk t i i i i ? + + + + ? ) _ _ the minimum size of bootstrap capacitor is: bs tot boot v q c ? = min an example follows: using a 15a @ 100c igbt (gb15xp120k): ? i qbs = 250 a (see static electrical charact.); ? i lk = 50 a (see static electrical charact.); ? q ls = 20 nc; ? q g = 58 nc (q ge +q gc datasheet gb15xp120k); ? i lk_ge = 250 na (datasheet gb15xp120k); ? i lk_diode = 100 a (with reverse recovery time <100 ns); ? i lk_cap = 0 (neglected for ceramic capacitor); ? i ds- = 150 a (see static electrical charact.); ? t hon = 100 s. and: ? v cc = 18 v ? v f = 1 v ? v ceonmax = 2.5 v ? v gemin = 11.9 v the maximum voltage drop ? v bs becomes = ? ? ? ? ceon ge f cc bs v v v v v min downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 24 v v v v v 6.2 5.2 9.11 1 18 = ? ? ? = and the bootstrap capacitor must be: nf v nc c boot 51 6.2 133 = notice: here above v cc has been chosen to be 18v as an example. igbts can be supplied with higher/lower supply accordingly to design requirements. vcc variations due to low voltage power supply must be accounted in the above formulas. some important considerations a. voltage ripple there are three different cases making the bootstrap circuit get conductive (see figure 23) ? i load < 0; the load current flows in the low side igbt displaying relevant v ceon ceon f cc bs v v v v ? ? = in this case we have the lowest value for v bs . this represents the worst case for the bootstrap capacitor sizing. when the igbt is turned off the vs node is pushed up by the load current until the high side freewheeling diode get forwarded biased ? i load = 0; the igbt is not loaded while being on and v ce can be neglected f cc bs v v v ? = ? i load > 0; the load current flows through the freewheeling diode fp f cc bs v v v v + ? = in this case we have the highest value for v bs . turning on the high side igbt, i load flows into it and v s is pulled up. to minimize the risk of undervoltage, bootstrap capacitor should be sized according to the i load <0 case. b. bootstrap resistor a resistor (r boot ) is placed in series with bootstrap diode (see figure 23) so to limit the current when the bootstrap capacitor is initially charged. we suggest not exceeding some ohms (typically 5, maximum 10 ohm) to avoid increasing the v bs time- constant. the minimum on time for charging the bootstrap capacitor or for refreshing its charge must be verified against this time-constant. c. bootstrap capacitor for high t hon designs where is used an electrolytic tank capacitor, its esr must be considered. this parasitic resistance forms a voltage divider with r boot generating a voltage step on v bs at the first charge of bootstrap capacitor. the voltage step and the related speed (dv bs /dt) should be limited. as a general rule, esr should meet the following constraint: v v r esr esr cc boot 3 ? + parallel combination of small ceramic and large electrolytic capacitors is normally the best compromise, the first acting as fast charge thank for the gate charge only and limiting the dv bs /dt by reducing the equivalent resistance while the second keeps the v bs voltage drop inside the desired ? v bs . d. bootstrap diode the diode must have a bv> 600v (or 1200v depending on application) and a fast recovery time (trr < 100 ns) to minimize the amount of charge fed back from the bootstrap capacitor to v cc supply. 2.2 gate resistances the switching speed of the output transistor can be controlled by properly size the resistor s controlling the turn-on and turn-off gate current. the following section provides some basic rules for sizing the resistors to obtain the desired switching time and speed by introducing the equivalent output resistance of the gate driver ( r drp and r drn ). the examples always use igbt power transistor. figure 24 shows the nomenclature used in the following paragraphs. in addition, v ge * indicates the plateau voltage, q gc and q ge indicate the gate to collector and gate to emitter charge respectively. downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 25 v ge * 10% t 1 ,q ge c resoff c reson v ce i c v ge c res 10% 90% c res t don v ge dv/dt i c t 2 ,q gc t,q t r t sw figure 24: nomenclature 2.2.1 sizing the turn-on gate resistor - switching-time for the matters of the calculation included hereafter, the switching time t sw is defined as the time spent to reach the end of the plateau voltage (a total q gc + q ge has been provided to the igbt gate). to obtain the desired switching time the gate resistance can be sized starting from q ge and q gc , vcc , v ge * (see figure 25): sw ge gc avg t q q i + = and avg ge tot i v vcc r * ? = vcc/vb r drp r gon c res com/vs i avg figure 25: r gon sizing where gon drp tot r r r + = r gon = gate on-resistor r drp = driver equivalent on-resistance ir22381q/IR21381q hop/lop and hoq/loq pins can be used to configure gate charge circuit. fast turn on can be configured using hop and lop pins (up to t on1 switching time). for slower turn on times hoq and loq can be used. current partitioning can be changed acting on the output resistors. in particular, shorting hop to hoq and lop to loq, r drp is defined by ? ?? ? ?? ? > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + = + + + 1 1 1 1 2 1 1 1 on sw o on sw on sw o o sw on drp t t when i vcc t t when t t i vcc i vcc t t r (i o1+ ,i o2+ and t on1 from static electrical characteristics). table 1 reports the gate resi stance size for two commonly used igbts (calculation made using typical datasheet values and assuming vcc=15v). - output voltage slope turn-on gate resistor r gon can be sized to control output slope (dv out /dt) . while the output voltage has a non-linear behaviour, the maximum output slope can be approximated by: resoff avg out c i dt dv = inserting the expression yielding i avg and rearranging: dt dv c v vcc r out resoff ge tot ? ? = * as an example, table 2 shows the sizing of gate resistance to get dv out /dt=5v/ns when using two popular igbts, typical datasheet values and assuming vcc=15v . notice : turn on time must be lower than t bl to avoid improper desaturation detection and ssd triggering. downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 26 sizing the turn-off gate resistor the worst case in sizing the turn-off resistor r goff is when the collector of the igbt in off state is forced to commutate by external events (i.e. the turn-on of the companion igbt). in this case the dv/dt of the output node induces a parasitic current through c resoff flowing in r goff and r drn (see figure 26). if the voltage drop at the gate exceeds the threshold voltage of the igbt, the device may self turn on causing large oscillation and relevant cross conduction. off hs turning on on dv/dt r goff c resoff r drn c ies figure 26: r goff sizing: current path when low side is off and high side turns on the transfer function between igbt collector and igbt gate then becomes: ) () ( 1 ) ( ies resoff drn goff resoff drn goff de ge c c r r s c r r s v v + ? + ? + ? + ? = which yields to a high pass filter with a pole at: ) () ( 1 /1 ies resoff drn goff c c r r + ? + = as a result, when is faster than the collector rise time (to be verified after calculation) the transfer function can be approximated by: resoff drn goff de ge c r r s v v ? + ? = ) ( so that dt dv c r r v de resoff drn goff ge ? ? + = ) ( in the time domain. then the condition: ( ) dt dv c r r v v out resoff drn goff ge th ? + = > must be verified to avoid spurious turn on. rearranging the equation yields: (1) drn resoff th goff r dt dv c v r ? ? < in any case, the worst condition for a spurious turn on is with very fast steps on igbt collector. in that case collector to gate transfer function can be approximated with the capacitor divider: ) ( ies resoff resoff de ge c c c v v + ? = which is driven only by igbt characteristics. as an example, table 3 reports r goff (calculated with the above mentioned equation (1)) for two popular igbts to withstand dv out /dt = 5v/ns . notice: the above-described equations are intended being an approximated way for the gate resistances sizing. more accurate sizing may account more precise device modelling and parasitic component dependent on the pcb and power section layout and related connections. table 1: r gon sizing driven by t sw constraint igbt qge qgc vge* tsw iavg rtot rgon std commercial value tsw gb15xp120k* 12nc 46nc 9v 500ns 116ma 77 ? rtot - rdrp = 15 ? 10 ? 465ns gb05xp120k 3.7nc 14nc 9.5v 400ns 44ma 124 ? rtot - rdrp = 65 ? 68 ? 408ns irgb5b120kd 3.7nc 13nc 9.5v 500ns 33ma 164 ? rtot - rdrp = 102 ? 100 ? 502ns table 2: table 2: rgon sizing driven by dvout/dt constraint igbt qge qgc vge* cresoff rtot rgon std commercial value dvout/dt gb15xp120k* 12nc 46nc 9v 38pf 47 ? rtot - rdrp = 4.5 ? 4.7 ? 5v/ns gb05xp120k 3.7nc 14nc 9.5v 12pf 91 ? rtot - rdrp = 48.8 ? 47 ? 5.1v/ns irgb120kd 3.7nc 13nc 9.5v 11pf 100 ? rtot - rdrp = 57 ? 56 ? 5v/ns downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 27 table 3: rgoff sizing igbt vth(min) cresoff rgoff gb15xp120k* 5 38pf rgoff = 0 ? gb05xp120k 5 12pf rgoff 55 ? irg4ph20k(d) 5 11pf rgoff 63 ? * sized with 18v supply 3 pcb layout tips 3.1 distance from h to l voltage the ir22381/IR21381q pin out lacks some pins (see figure 17) maximizing the distance between floating (from dc- to dc+) and low voltage pins . its strongly recommended to place components tied to floating voltage in the respective high voltage portions of the device (vb 1,2,3 , vs 1,2,3 ) side. 3.2 ground plane ground plane must not be placed under or nearby the high voltage floating side to minimize noise coupling. 3.3 gate drive loops current loops behave like an antenna able to receive and transmit em noise. in order to reduce em coupling and improve the power switch turn on/off performances, gate drive loops must be reduced as much as possible. figure 23 shows the high and low side gate loops. moreover, current can be injected inside the gate drive loop via the igbt collector-to-gate parasitic capacitance. the parasitic auto-inductance of the gate loop contributes to develop a voltage across the gate-emitter increasing the possibility of self turn-on effect. for this reason is strongly recommended to place the three gate resistances close together and to minimize the loop area (see figure 27). figure 27: gate drive loop 3.4 supply capacitors ir22381 output stages are able to quickly turn on igbt with up to 460ma of output current. the supply capacitors must be placed as close as possible to the device pins (v cc and v ss for the ground tied supply, v b and v s for the floating supply) in order to minimize parasitic inductance/resistance. 3.5 routing and placement example figure 28 shows one of the possible layout solutions using a 3 layer pcb (low voltage signals not shown) on an econo pim module. this example takes into account all the previous considerations. placement and routing for supply capacitors and gate resistances in the high and low voltage side minimize respectively supply path and gate drive loop. the bootstrap diode is placed under the device to have the cathode as close as possible to bootstrap capacitor and the anode far from high voltage and close to v cc . downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 28 a) top(gate drive) b) bottom (gnd) downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 29 c) mid (vcc/com/dcp) figure 28: layout example: top (a), internal layer (b) and bottom (c) layer downloaded from: http:///
ir22381q pbf /IR21381q ( p b f ) 30 case o u t l ine qualification level: industrial level, msl3, lead-free. esd classification: human body model (hbm): class 2, per jesd22-a114-b machine model (mm): class b, per eia/jesd22-a115-a world headquarters: 233 kansas st., el segundo, ca lifornia 90245 tel: (310) 252-7105 this product has been qualified for the industrial market. data and specif i c atio n s are s ubj e c t to cha n ge wit h out notice. 08/11 /05. downloaded from: http:///

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